Time to Digital Converter – 1ns 5ch – Low-Pin-Count
An FPGA Mezzanine Card (FMC) with a Time to Digital Converter chip to perform one-shot sub-nanosecond time interval measurements.
Main Features
- 5 inputs, TTL with software selectable 50 Ohm termination.
- LEMO 00 connectors for all inputs.
- External inputs need to be protected against +15V pulses with a pulse width of at least 10us@50Hz.
- Time tags apply to rising edges of inputs.
- TDC Chip: ACAM TDC-GPX multifunctional High-end Time-to-Digital Converter
- Accuracy (of time-tag differences between channels): +/- (250 ps + timebase accuracy).
- Timebase accuracy: +/- 4ppm.
- Implementation details: timebase from a local TCXO on FMC card and needs calibration.
- Much better accuracy will be reached when used on a White Rabbit enabled FMC carrier.
- Minimum input pulse width: 100 ns. Narrower pulses should be ignored.
- Programmable (enable/disable) host interrupts on all 5 channels.
- 6-layer PCB.
- FMC mezzanine using a Low Pin Count (LPC) connector.
- Vadj 2.5V or higher.
- Open Hardware (Published under CERN OHL)
A circular buffer will contain time tags for at least the last 100 input pulses. These time tags will at first be rough UTC (counter initialized by SW) giving ~ms accuracy. Later, with a WR-enabled solution, they can be much more accurate. Differences between channels will not suffer from this accuracy problem because the offset with respect to UTC will cancel.
