Side View of FMC Fine DelayFine delay 1ns 4cha – Low-Pin-Count

An FPGA Mezzanine Card (FMC) created to produce pulses delayed by a user-programmed value with respect to the input trigger pulse. It has 4 output channels and one input trigger. The delay from the trigger input to each of the outputs can be set independently in a range from 600 ns to 120 seconds. It is implemented using a dedicated time-to-digital converter IC from the European company Acam.

Main Features

  • LEMO 00 connectors for all input/outputs.
  • FMC mezzanine using a Low Pin Count (LPC) connector.
  • TTL, outputs capable of driving a 50 Ohm load, > 2 V/ns slew rate
  • TDC Chip: ACAM TDC-GPX multifunctional High-end Time-to-Digital Converter
  • Timing: +/- 2.5 ppm on-board oscillator accuracy, or WR master oscillator accuracy
  • 1 inputs, TTL/LVTTL3.3 with software selectable 2kOhm/50 Ohm termination.
    • need to be protected against +5V[1] pulses with a pulse width of at least 10us@50Hz.
    • Timing: 20ns maximum input pulse edge rise time; Minimum pulse width tIW = 50 ns: Pulses below 24 ns are rejected; 1Mhz bandwidth;
  • 4 outputs, TTL-compatible levels DC-coupled:
    • Voh = 3 V, Vol = 200 mV (50 Ohm load), Voh = 6V, Vol = 400 mV (high impedance).
    • Rise/fall: 2.5ns; Power-up state: LOW (2 kOhm pulldown), guaranteed glitch-free
    • 10ps resolution; Pulse generator mode accuracy 300 ps.
    • Output-to-output jitter 10 ps rms; 80 ps rms trigger-to-output jitter
    • 100 ns – 16 s output pulse spacing
  • 6-layer PCB.
  • Vadj 2.5V or higher.

The board can work in the following modes:

  • Pulse Delay: produces one or more pulse(s) on selected outputs a given time after an input trigger pulse.
  • Pulse Generator: produces one or more pulse(s) on selected outputs starting at an absolute time value programmed by the user. In this mode, time base is usually provided by the White Rabbit network.
  • Time to Digital Converter: tags all trigger pulses and delivers the timestamps to the user’s application.

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Back View of FMC Fine Delay

Back View of FMC Fine Delay