The FmcAdc100M14b4cha is a 4 channel 100MSPS 14 bit ADC card in FMC (FPGA Mezzanine Card) format. By default it uses only signals from the LPC rows of the HPC connector that is mounted. The gain can be set by software in three steps: +/-50mV, +/-0.5V, +/-5V. An advanced offset circuit is used in the front-end design of the ADC board, and allows a voltage shift in the range of +/- 5V that is independent on the chosen gain range.
| Parameter | Value |
|---|---|
| max. sample rate | 105 MSPS (default 100MSPS) |
| analog bandwidth | 30 MHz. DC-coupled (40 MHz possible by changing eight capacitors) |
| bits/sample | 14 bit |
| ENOB | 11.0, 11.5, 11.7 bit (@ +/-50mV, +/-0.5V, +/-5V range) |
| SNR | 67.7 dB, 70.8 dB, 72.2 dB (@ +/-50mV, +/-0.5V, +/-5V range) |
| channels | 4 |
| connectors | 4 x LEMO 00 for signals, 1 x LEMO 00 for trigger |
| input impedance | 1 kOhm / 50 Ohm – software selectable |
| gain steps | +/-50 mV +/-0.5 V +/-5 V |
| offset correction range | +/- 5 V for every input voltage range |
| max. gain error | +/- 1 % |
| FMC to carrier interface | FMC high pin count connector (HPC only used if external clock is selected) |
| Clock source | Internal: from programmable on-board oscillator. External: from dedicated FMC connector pins (HPC) when changing two capacitors. |
2017 measurements
Channel 1
| Parameter | Value |
|---|---|
| ENOB | 9.3, 10.7, 10.8 bit (@ +/-50mV, +/-0.5V, +/-5V range) |
| SNR | 58.2 dB, 66.6 dB, 67.5 dB (@ +/-50mV, +/-0.5V, +/-5V range) |
Channel 2-4 (worst case)
| Parameter | Value |
|---|---|
| ENOB | 9.3, 11.0, 11.2 bit (@ +/-50mV, +/-0.5V, +/-5V range) |
| SNR | 58.2 dB, 68.4 dB, 69.6 dB (@ +/-50mV, +/-0.5V, +/-5V range) |
Pleas see the full project on the CERN open hardware repository here: