FMC-ADC500-5, ADC FMC HPC, 500MS/s 16bits

Click for full size image

FMC-ADC500-5 is a High Pin Count (HPC) FMC module with 5 ADC channels each running at up to 500MS/s with a dynamic range of 16 bits. The module has 5 ADC31JB68 ICs from Texas Instruments together with an HMC7044 from ADI which is the source of clocks feeding the ADCs. Provision for external clock input is also provided for this hardware.

An internal VCXO and TCXO clock are the input to HMC7044 and with 5 clock outputs to the ADCs. HMC7044 offers a SYSREF clock with known and adjustable delay which can be sent to the FPGA as REF CLK and SYSREF CLK, to achieve requirement of subclass 1 JESD204B. The external clock input can be used as Device clock for ADCs, or as reference clock.

ADC input signal bandwidth is 4.5 to 250MHz while the external clock bandwidth is 10 to 800Mhz, when used as reference clock, and 400 to 4000Mhz when used as device clock. Trigger maximum voltage will be 6V on this module.

External trigger input allows to add a time stamps to the sample stream from ADCs. CLK IN can be a Sample clock input up to 4GHz, or reference clock input up to 800MHz. Board clocking structure provide possibility of deterministic latency and subclass 1 synchronization between multiple ADCs.

This module can be expanded/pipelined using additional FPGAs cards if necessary.

FMC-ADC500-5 is supported by Sundance DSP PXIe700, PXIe and PCIe FPGA boards using Xilinx Kintex series.  Our PXIe700 and PCIe-K800 are 100% user programmable with an open FPGA that enables users to implement their proprietary signal pre-processing algorithms.

ADC Parameters

Clock and trigger-in parameters

Features

Applications