The vi020 is a COTS integration combining the power of an Altera Stratix® V FPGA and Texas Instruments KeyStone Multicore DSP openVPX carrier (VF360) with a fine delay module (TSS-2000)

Key points of the module:

  • LEMO 00 connectors for all input/outputs.
  • FMC mezzanine using a Low Pin Count (LPC) connector.
  • TTL, outputs capable of driving a 50 Ohm load, > 2 V/ns slew rate
  • TDC Chip: ACAM TDC-GPX multifunctional High-end Time-to-Digital Converter
  • Timing: +/- 2.5 ppm on-board oscillator accuracy, or WR master oscillator accuracy
  • 1 inputs, TTL/LVTTL3.3 with software selectable 2kOhm/50 Ohm termination.
    • need to be protected against +5V[1] pulses with a pulse width of at least 10us@50Hz.
    • Timing: 20ns maximum input pulse edge rise time; Minimum pulse width tIW = 50 ns: Pulses below 24 ns are rejected; 1Mhz bandwidth;
  • 4 outputs, TTL-compatible levels DC-coupled:
    • Voh = 3 V, Vol = 200 mV (50 Ohm load), Voh = 6V, Vol = 400 mV (high impedance).
    • Rise/fall: 2.5ns; Power-up state: LOW (2 kOhm pulldown), guaranteed glitch-free
    • 10ps resolution; Pulse generator mode accuracy 300 ps.
    • Output-to-output jitter 10 ps rms; 80 ps rms trigger-to-output jitter
    • 100 ns – 16 s output pulse spacing
  • 6-layer PCB.
  • Vadj 2.5V or higher.

The board can work in the following modes:

  • Pulse Delay: produces one or more pulse(s) on selected outputs a given time after an input trigger pulse.
  • Pulse Generator: produces one or more pulse(s) on selected outputs starting at an absolute time value programmed by the user. In this mode, time base is usually provided by the White Rabbit network.
  • Time to Digital Converter: tags all trigger pulses and delivers the timestamps to the user’s application.

Key points of the OpenVPX carrier:

Processing FPGA:

  • Stratix V family in the KF40 (1517 FBGA) package
    • GX Device variants: 5SGXA3, 5SGXA4, 5SGXA5, 5SGXA7, 5SGXA9 and 5SGXAB
    • GS Device variants: 5SGSD4, 5SGSD5, 5SGSD6 and 5SGSD8
  • Embedded device memory: 19-52 Mb
  • Embedded device multipliers (18×18): 512 – 3,926
  • DDR3 and QDRII+ external memory
    • Up to 2GB DDR3 @ 667MHz (arranged as two 256M x 32-bit banks), default 1GB
    • Up to 32MB QDRII+ SRAM @ 400MHz (arranged as two 8M x 18-bit banks), default 16MB

Digital Signal Processing:

  • TI KeyStone Multicore C667x family of processors
    • Up to 8 cores @ 1.2 GHz
  • External memory:

FPGA Mezzanine Card (FMC-HPC):

  • 10x High-Speed Serial Interface lanes
  • LVDS interface on LA and HA

VPX Interface:

  • Complies with OpenVPX MOD3-PAY-3F2U-16.2.12-2 module profile
    • PCIe Gen2 Data plane (3x Fat Pipes)
    • GigE 1000BASE-BX Control plane (2x Ultra-Thin Pipes)
    • Payload module with System Controller capability
  • Supports FPGA configurable User I/O on P2
    • 24x single-ended 2.5V LVCMOS I/Os
    • 10x High-Speed Serial Interface lanes