vi922 – 1Ch. ADC & 2Ch. DAC

The vi922 is a COTS integration combining the power of an Altera Stratix® V FPGA and Texas Instruments KeyStone Multicore DSP openVPX carrier (VF360) with a DAQ module – SMT-FMC331

Key points of the DAQ module:

  • ADC12J2700 – 12bit 2.7GSPS JESD204B.
  • LM95233 for ADC temperature monitoring.
  • JESD204B via HPC connector, 8 lanes 5.4Gbps per lane.
  • AD9136 – 16-bit dual channel 2.8GSPS JESD204B DAC.
  • HMC7044 – High performance 3.2GHz JESD204B jitter attenuator.
  • 3 Input connectors type SSMC:
    • One for single ended input of ADC signal, up to 2.7GHz.
    • One connector for trigger input(logic level).
    • One for clock input(can be used as Device clock for ADC and DAC, and can be used as reference clock for ADC and DAC)
  • 2 output connectors for DAC output, type SSMC.
  • JESD204B Subclass 1 capable.
  • 100 MHz onboard VCXO.
  • 2 Tx and Rx High speed lanes available on additional Molex nano-pitch connector.
  • 2 Additional LVDS lines from FMC connector available via Molex nano-pitch connector.
  • 2 Clock signals and Vadj power supply available on Molex nano-pitch connector.
  • I2C from FMC connector available via Molex nano-pitch connector.
  • Vadj supported voltages:1.8V, 2.5V, 3.3V
  • Power consumptions: 12V – max 1.1A , 3.3V – max 0.6A, Vadj – max 0.1A

Key points of the OpenVPX carrier:

Processing FPGA:

  • Stratix V family in the KF40 (1517 FBGA) package
    • GX Device variants: 5SGXA3, 5SGXA4, 5SGXA5, 5SGXA7, 5SGXA9 and 5SGXAB
    • GS Device variants: 5SGSD4, 5SGSD5, 5SGSD6 and 5SGSD8
  • Embedded device memory: 19-52 Mb
  • Embedded device multipliers (18×18): 512 – 3,926
  • DDR3 and QDRII+ external memory
    • Up to 2GB DDR3 @ 667MHz (arranged as two 256M x 32-bit banks), default 1GB
    • Up to 32MB QDRII+ SRAM @ 400MHz (arranged as two 8M x 18-bit banks), default 16MB

Digital Signal Processing:

  • TI KeyStone Multicore C667x family of processors
    • Up to 8 cores @ 1.2 GHz
  • External memory:

FPGA Mezzanine Card (FMC-HPC):

  • 10x High-Speed Serial Interface lanes
  • LVDS interface on LA and HA

VPX Interface:

  • Complies with OpenVPX MOD3-PAY-3F2U-16.2.12-2 module profile
    • PCIe Gen2 Data plane (3x Fat Pipes)
    • GigE 1000BASE-BX Control plane (2x Ultra-Thin Pipes)
    • Payload module with System Controller capability
  • Supports FPGA configurable User I/O on P2
    • 24x single-ended 2.5V LVCMOS I/Os
    • 10x High-Speed Serial Interface lanes