The vi828 is a COTS integration combining the power of an Altera Stratix® V FPGA and Texas Instruments KeyStone Multicore DSP openVPX carrier (VF360) with a 6 channel ADC (FM581)
Key points of the ADC module:
- 3x Texas Instruments ASC16DX370 Dual ADCs
- SNR: 69 dBFS with AIN = 231 MHz
- SFDR: 85 dBFS with AIN = 231 MHz
- Sampling resolution: 16 bits
- Front panel input connectors
- Analogue Inputs
- Six single ended AC coupled analogue inputs
- RF input bandwidth (-3 dB): 800MHz
- Full scale input power: +7 dBm (1.4 Vpp)
- Input impedance: 50 Ohm
- Clock Input
- Single ended AC coupled LVPECL/LVDS
- Frequency range: 50 – 370 MHz
- Input Voltage: sine or square wave (1V p-p)
- Input impedance: 50 Ohm
- Trigger Input
- Single ended DC coupled LVPECL/LVTTL
- Input impedance: 50 Ohm
- Analogue Inputs
- FMC Interface
- 6x JESD204B interfaces for digitized samples
- SPI interface from ADC configuration
- Discrete control lines
- Firmware and Support Software
- FDK for custom firmware development on VF360
- SDK with LINUX driver and example application
- Firmware development services available on request.
Key points of the OpenVPX carrier:
Processing FPGA:
- Stratix V family in the KF40 (1517 FBGA) package
- GX Device variants: 5SGXA3, 5SGXA4, 5SGXA5, 5SGXA7, 5SGXA9 and 5SGXAB
- GS Device variants: 5SGSD4, 5SGSD5, 5SGSD6 and 5SGSD8
- Embedded device memory: 19-52 Mb
- Embedded device multipliers (18×18): 512 – 3,926
- DDR3 and QDRII+ external memory
- Up to 2GB DDR3 @ 667MHz (arranged as two 256M x 32-bit banks), default 1GB
- Up to 32MB QDRII+ SRAM @ 400MHz (arranged as two 8M x 18-bit banks), default 16MB
Digital Signal Processing:
- TI KeyStone Multicore C667x family of processors
- Up to 8 cores @ 1.2 GHz
- External memory:
FPGA Mezzanine Card (FMC-HPC):
- 10x High-Speed Serial Interface lanes
- LVDS interface on LA and HA
VPX Interface:
- Complies with OpenVPX MOD3-PAY-3F2U-16.2.12-2 module profile
- PCIe Gen2 Data plane (3x Fat Pipes)
- GigE 1000BASE-BX Control plane (2x Ultra-Thin Pipes)
- Payload module with System Controller capability
- Supports FPGA configurable User I/O on P2
- 24x single-ended 2.5V LVCMOS I/Os
- 10x High-Speed Serial Interface lanes