vi921- 12Ch. ADC & 2Ch. DAC

The vi911 is a COTS integration combining the power of an Altera Stratix® V FPGA and Texas Instruments KeyStone Multicore DSP openVPX carrier (VF360) with a 14 channel DAQ module – FMC-FADB

Key points of the DAQ module:

  • FMC HPC Connector (high-pin count with 400 pin high-speed array connector)
    • 8 ADC channels are compatible with FMC LPC
  • QSE Connector Compatible with Samtec EQRF
    • 12x (3×4) ADC input channels @ 125Msps / 14-bits
    • 2x ouput DAC channels @ 1.25 Gsps / 16-bits
    • 1x optional input clock channel for PLL.
    • 1x output clock channel given by PLL. 
  • 3x ADC Chips from Linear Technology: LTC2175-14
    • 14-bit & 125Msps
    • 4 simultaneous sample channels per chip
    • 73.1 dB SNR / 88 dB SFDR
    • Input Levels: [1-2] Vpp
    • 800MHz hold & sample bandwidth
  • 1x DAC chip from Texas Instruments: DAC3482
    • 16-bits & 1.25 Gsps
    • 2 channels per chip
    • Selectable 2x, 4x, 8x, 16x Interpolation Filter
    • Digital I and Q Correction
    • Differential Scalable Output: 10mA to 30mA
  • AD-9516 PLL
    • Selectable external input clock or FGPA clock
    • Output LVDS clock
    • On-Chip VXCO: [2.55-2.9] Ghz
    • Channel-to-channel skew paired outputs of <10 ps
    • Additive output jitter: 275 fs rms LVDS (ADC) / 225 fs rms LVPECL (DAC)
  • Samtec EQRF features (optional):
    • Choice of SMA, MCX or MMCX RF termination
    • RG 316 or RG 178 cable

Key points of the OpenVPX carrier:

Processing FPGA:

  • Stratix V family in the KF40 (1517 FBGA) package
    • GX Device variants: 5SGXA3, 5SGXA4, 5SGXA5, 5SGXA7, 5SGXA9 and 5SGXAB
    • GS Device variants: 5SGSD4, 5SGSD5, 5SGSD6 and 5SGSD8
  • Embedded device memory: 19-52 Mb
  • Embedded device multipliers (18×18): 512 – 3,926
  • DDR3 and QDRII+ external memory
    • Up to 2GB DDR3 @ 667MHz (arranged as two 256M x 32-bit banks), default 1GB
    • Up to 32MB QDRII+ SRAM @ 400MHz (arranged as two 8M x 18-bit banks), default 16MB

Digital Signal Processing:

  • TI KeyStone Multicore C667x family of processors
    • Up to 8 cores @ 1.2 GHz
  • External memory:

FPGA Mezzanine Card (FMC-HPC):

  • 10x High-Speed Serial Interface lanes
  • LVDS interface on LA and HA

VPX Interface:

  • Complies with OpenVPX MOD3-PAY-3F2U-16.2.12-2 module profile
    • PCIe Gen2 Data plane (3x Fat Pipes)
    • GigE 1000BASE-BX Control plane (2x Ultra-Thin Pipes)
    • Payload module with System Controller capability
  • Supports FPGA configurable User I/O on P2
    • 24x single-ended 2.5V LVCMOS I/Os
    • 10x High-Speed Serial Interface lanes
VI921