The vi717 is a COTS integration combining the power of an Altera Stratix® V FPGA and Texas Instruments KeyStone Multicore DSP openVPX carrier (VF360) with a two channel DAC board – FMC230
Key points of the DAC module:
- Two AD9129: 2-channel 14-bit D/A up to 5.7 Gsps (2.85Gsps without 1:2 interpolation) – LVDS
- VITA 57.1-2010 compliant
- Conduction Cooled – Standard Option
- Single ended AC-coupled analog signals.
- 6 MMCX/SSMC connectors available from the front panel
- Clock Source, Sampling Frequency, and Calibration through a SPI communication busses
- Flexible clock tree enables:
- on board VCO: 2300MHz – 2650MHz
- external reference clock
- external sampling clock
- Power-down modes to switch off unused functions for system power savings
- Mil-I-46058c Conformal Coating Compliant (optional)
- HPC – High Pin Count Connector
- LVDS IO signalling
Key points of the OpenVPX carrier:
Processing FPGA:
- Stratix V family in the KF40 (1517 FBGA) package
- GX Device variants: 5SGXA3, 5SGXA4, 5SGXA5, 5SGXA7, 5SGXA9 and 5SGXAB
- GS Device variants: 5SGSD4, 5SGSD5, 5SGSD6 and 5SGSD8
- Embedded device memory: 19-52 Mb
- Embedded device multipliers (18×18): 512 – 3,926
- DDR3 and QDRII+ external memory
- Up to 2GB DDR3 @ 667MHz (arranged as two 256M x 32-bit banks), default 1GB
- Up to 32MB QDRII+ SRAM @ 400MHz (arranged as two 8M x 18-bit banks), default 16MB
Digital Signal Processing:
- TI KeyStone Multicore C667x family of processors
- Up to 8 cores @ 1.2 GHz
- External memory:
FPGA Mezzanine Card (FMC-HPC):
- 10x High-Speed Serial Interface lanes
- LVDS interface on LA and HA
VPX Interface:
- Complies with OpenVPX MOD3-PAY-3F2U-16.2.12-2 module profile
- PCIe Gen2 Data plane (3x Fat Pipes)
- GigE 1000BASE-BX Control plane (2x Ultra-Thin Pipes)
- Payload module with System Controller capability
- Supports FPGA configurable User I/O on P2
- 24x single-ended 2.5V LVCMOS I/Os
- 10x High-Speed Serial Interface lanes